The present invention relates to an arrangement and to a method for encoding serial data using block codes, and to an arrangement and method for serial-parallel conversion and decoding of encoded data respectively, and to a transmission system, particularly a multi-channel fibre-optics system, utilizing said encoding facility on at least one transmitter side and said decoding facility on at least one receiver side.
Encoding of a serial data bit stream using block codes, particularly channel encoding, can be effected by dividing the data bit stream into words or blocks, wherein there is added to each block a number of check bits which are solely dependent on the data bits within the block.
Encoding is often effected by serial-parallel conversion at the input of an encoder, followed by the performance of logic operations, i.e. the actual encoding process in which the check bits are added. Finally, parallel-serial conversion is effected at the encoder output. A clock pulse is used for triggering the read-in of the serial bit stream at the input, i.e. read-in occurs at each positive or negative edge of the clock pulse.
However, it is difficult to implement block coding at high transmission speeds, for instance in optical high speed systems in the Gbit/s range. It is particularly difficult to implement a simple encoding logic operation and synchronising logic operation which will allow high speeds. Serial-parallel conversion and parallel-serial conversion respectively can also constitute limiting factors. Furthermore, there is required an encoding process which is not highly demanding with respect to lower and upper cut-off frequencies in regard of amplifiers included in the transmission system.
Among other things, this requires encoding that will retain a d.c. stability, particularly in the case of optical high-speed transmissions, i.e. encoding which contains roughly the same number of ones as zeros, and encoding where the maximum number of consecutive symbols of the same kind, for instance ones or zeros, is low.
The object of the present invention is to provide an arrangement and a method for encoding and decoding at high transmission rates, particularly in the Gbit/s range, using block codes to this end.
This is achieved by encoding a serial bit stream of input data in groups of N bits to serial encoded data in groups of 2N bits with the aid of an encoder which includes a serial-parallel converter, a logic circuit and a parallel-serial converter. Decoding is effected with a decoder that includes a serial-parallel converter, a logic circuit, a comparitor and a parallel-serial converter.
The encoder logic circuit is so constructed that N of the 2N bits of encoded data are comprised of the N bits input data, either unchanged or inverted, wherein remaining bits are determined such that, seen statistically, the groups of encoded data will include roughly as many zeros as ones, wherein each group of encoded data is unique for each group of non-encoded data, and wherein at least one of the groups of encoded data remains unique in shifting processes in the bit stream.
The decoder is constructed so that the encoded words are read-in and serial-parallel converted. The N bits of non-encoded data are separated and encoded one more time. This is effected in the decoder logic circuit, which is identical to the aforedescribed encoder logic circuit. The code words encoded in the decoder logic circuit are compared with the code words incoming to the decoder. When the comparison shows a predetermined result, the non-coded data separated from the N bits is parallel-serial converted.
Another object of the invention is to provide simple unsynchronized read-in and serial-parallel conversion of encoded data when decoding.
A third object of the invention is to enable the serial-parallel conversion process to use in decoding a clock pulse or clock signal of the same frequency as that used when encoding.
There is preferably used a serial-parallel converter which utilizes both positive and negative edges of a clock signal for clocking, and whose frequency is half the value of the bit rate of the encoded serial bit stream. The serial-parallel converter will also conveniently be adapted to read all bits in the serial bit stream, and to carry out complete demultiplexing of the 2N bits last read-in for each bit that is read-in.
Such a serial-parallel converter can be implemented, for instance, with the aid of a first shift register and a second shift register arranged in parallel therewith, each register including 2N latches and 2N selectors. The latches in the first shift register are adapted to be clocked alternately at a low level clock signal, beginning with the first, and alternately at a high level clock signal. The latches in the second shift register are adapted to be clocked alternately at a low level clock signal, beginning with the second and alternately at a high level clock signal. The selectors are preferably adapted to select data from those latches that are not clocked after each edge of the clock signal.
One advantage with the invention is that it provides simple and reliable encoding and decoding even at high and very high transmission speeds.
Another advantage with the invention is that complete demultiplexing is carried out for each bit read into the decoder. This simplifies the read-in of encoded data and no prior synchronisation need be achieved.
Still another advantage of the invention is that the decoder is able to use both edges of a clock signal, and consequently both the encoder and the decoder can be implemented with clock signals of mutually the same frequency.
Yet another advantage of the invention is that low demands are placed on the lower cut-frequency of amplifiers in the system, because d.c. stability is maintained and because the maximum number of consecutive symbols, i.e. ones or zeros, is limited.